[PD-cvs] pd/src desire.c,1.1.2.217.2.114,1.1.2.217.2.115

[Mathieu Bouchard]

Update of /cvsroot/pure-data/pd/src
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv15142

Modified Files:
      Tag: desiredata
	desire.c 
Log Message:
.


Index: desire.c
===================================================================
RCS file: /cvsroot/pure-data/pd/src/Attic/desire.c,v
retrieving revision 1.1.2.217.2.114
retrieving revision 1.1.2.217.2.115
diff -C2 -d -r1.1.2.217.2.114 -r1.1.2.217.2.115
*** desire.c	4 Jan 2007 23:21:22 -0000	1.1.2.217.2.114
--- desire.c	5 Jan 2007 01:53:25 -0000	1.1.2.217.2.115
***************
*** 198,202 ****
  // when this becomes too small, use a bigger constant or a better impl.
  
! #define QUEUE_SIZE 1024
  struct t_queue {
  	int start,len;
--- 198,202 ----
  // when this becomes too small, use a bigger constant or a better impl.
  
! #define QUEUE_SIZE 4096
  struct t_queue {
  	int start,len;
***************
*** 3189,3197 ****
      else {
          const int vecsize = outsig->vecsize;
!             /* if the outsig->v is aligned the x->read will also be... */
! 	    if(vecsize&7) dsp_add(vinlet_perform, 3, x, outsig->v,vecsize);
! 	    else if(SIMD_CHECK1(n,outsig->v))
! 	         dsp_add(vinlet_perfsimd, 3, x, outsig->v,vecsize);
! 	    else dsp_add(vinlet_perf8,    3, x, outsig->v,vecsize);
          x->read = x->buf;
      }
--- 3189,3197 ----
      else {
          const int vecsize = outsig->vecsize;
! 	/* if the outsig->v is aligned the x->read will also be... */
! 	if(vecsize&7) dsp_add(vinlet_perform, 3, x, outsig->v,vecsize);
! 	else if(SIMD_CHECK1(n,outsig->v))
! 	     dsp_add(vinlet_perfsimd, 3, x, outsig->v,vecsize);
! 	else dsp_add(vinlet_perf8,    3, x, outsig->v,vecsize);
          x->read = x->buf;
      }
***************
*** 3258,3265 ****
              x->fill = x->endbuf - (x->hop - prologphase * re_parentvecsize);
              if (upsample * downsample == 1)
!                     dsp_add(vinlet_doprolog, 3, x, insig->v, re_parentvecsize);
              else {
!               resamplefrom_dsp(&x->updown, insig->v, parentvecsize, re_parentvecsize, x->updown.method);
!               dsp_add(vinlet_doprolog, 3, x, x->updown.v, re_parentvecsize);
              }
              /* } IOhannes */
--- 3258,3265 ----
              x->fill = x->endbuf - (x->hop - prologphase * re_parentvecsize);
              if (upsample * downsample == 1)
!                 dsp_add(vinlet_doprolog, 3, x, insig->v, re_parentvecsize);
              else {
!                 resamplefrom_dsp(&x->updown, insig->v, parentvecsize, re_parentvecsize, x->updown.method);
!                 dsp_add(vinlet_doprolog, 3, x, x->updown.v, re_parentvecsize);
              }
              /* } IOhannes */
***************
*** 3267,3272 ****
                 to free it here because we didn't in ugen_doit(). */
              if (!insig->refcount) signal_makereusable(insig);
!         }
!         else memset((char *)(x->buf), 0, bufsize * sizeof(*x->buf));
          x->directsignal = 0;
      } else {
--- 3267,3271 ----
                 to free it here because we didn't in ugen_doit(). */
              if (!insig->refcount) signal_makereusable(insig);
!         } else memset((char *)(x->buf), 0, bufsize * sizeof(*x->buf));
          x->directsignal = 0;
      } else {