[PD-dev] makefile template

[Hans-Christoph Steiner]

On Oct 17, 2011, at 12:08 PM, IOhannes m zmoelnig wrote:

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> On 2011-10-17 17:11, Patrice Colet wrote:
>> Hello IOhannes,
>>
>> all I could say is this:
>>
>> $ make -p -n | grep CXX
>> make: *** No targets specified and no makefile found.  Stop.
>> LINK.cc = $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(LDFLAGS) $(TARGET_ARCH)
>> COMPILE.cc = $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c
>> CXX = g++
>
> what do you mean by that?
> why does it mean that you have to manually add a "CXX=g++" line to  
> your
> Makefile?
> here (on linux), i get approximately the same.
> note that there is a line "CXX = g++" is the following output, though
> this is set implicitely by make and not explicitely in the makefile.
>
> <snip>
> $ make -p -n | grep CXX
> ALL_CXXFLAGS := -I"/usr/include/pd" -DPD -DVERSION='"0.0"' -fPIC -Wall
> - -W -g -O6 -funroll-loops -fomit-frame-pointer
> CXXFLAGS = -Wall -W -g
> LINK.cc = $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(LDFLAGS) $(TARGET_ARCH)
> OPT_CXXFLAGS = -O6 -funroll-loops -fomit-frame-pointer
> COMPILE.cc = $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c
> CXX = g++
>        $(CXX) $(ALL_CXXFLAGS) -o "$*.o" -c "$*.cpp"
>        $(CXX) $(ALL_LDFLAGS) -o "$*.$(EXTENSION)" "$*.o"  $(ALL_LIBS)
> $(SHARED_LIB)
>        $(CXX) $(ALL_LDFLAGS) -o "$*.$(EXTENSION)" "$*.o"  $(ALL_LIBS)
> $(SHARED_LIB)
>        $(CXX) $(ALL_LDFLAGS) -o $(LIBRARY_NAME).$(EXTENSION)
> $(SOURCES:.cpp=.o) $(LIBRARY_NAME).o $(ALL_LIBS)
>        @echo "CXX: $(CXX)"
>        @echo "CXXFLAGS: $(CXXFLAGS)"
>        @echo "ALL_CXXFLAGS: $(ALL_CXXFLAGS)"
>        $(CXX) $(ALL_CXXFLAGS) -o "$*.o" -c "$*.cpp"
> </snip>


MinGW does not include a 'cc.exe' only a 'gcc.exe'.  CC defaults to  
'cc', so for what we are doing, it makes sense to do CC=gcc.  It looks  
like MinGW's default CXX is g++ and MinGW includes a 'g++.exe' so  
there is no need to set CXX in the Makefile.

>> There another thing very unlikely in template/Makefile, if do a  
>> 'make clean', it removes all the sources as well as objects and  
>> binaries
>> so for not loosing sources I have to remove these lines:
>>
>> -rm -f -- $(SOURCES:.cpp=.o) $(SOURCES_LIB:.cpp=.o) $ 
>> (SHARED_SOURCE:.cpp=.o)
>> -rm -f -- $(SOURCES:.cpp=.$(EXTENSION))
>
>
> then you did something weird :-)
> i had the same problem after changing CC to CXX and replacing  
> myobject.c
> with myobject.cpp
>
> the template/Makefile is full of assumptions that the sources end with
> ".c"; to compile .cpp files, you will have to replace all the pattern
> substitutions throughout the makefile from %.c to %.cpp
> mainly you will find this in constructs like "$(SOURCES:.c=.o)" which
> need to be changed to "$(SOURCES:.cpp=.o)"



Yes, that's what's causing everything to get deleted.  Basically  
".c=.o" means replace a ".c" ending with ".o".  If there isn't a ".c"  
ending, it just passes the values thru unchanged.  Since the  
myobject.cpp doesn't end in ".c", it passes thru unchanged, and  
therefore 'make clean' is deleting myobject.cpp rather than myobject.o.

.hc

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