[PD-dev] About inlet DSP prolog.

[Nicolas Danet]

I implemented a lock-free logger in my fork that i use for instance to report the DSP scheduling step by step. 

< https://github.com/Spaghettis/Spaghettis/blob/master/src/dsp/graph/d_vinlet.c#L123 >

I have catch the problem while testing edge cases.

----- Mail d'origine -----
De: Miller Puckette <msp at ucsd.edu>
À: Nicolas Danet <nicolas.danet at free.fr>
Cc: pd-dev at lists.iem.at
Envoyé: Sun, 05 Aug 2018 04:23:06 +0200 (CEST)
Objet: Re: [PD-dev] About inlet DSP prolog.

This seems to fix teh problem.  I don't know how you or anyone (myself
included) can understand how that code works...

cheers
Miller

On Wed, Feb 14, 2018 at 07:49:19AM +0100, Nicolas Danet wrote:
> Hi,
> 
> < https://github.com/pure-data/pure-data/blob/master/src/g_io.c#L210 >
> 
> x->x_fill = x->x_endbuf - (x->x_hop - prologphase * re_parentvecsize);
> 
> < g.io.c / line 210 >
> 
> IMHO it does not properly shift the buffer in case of overlap (i.g. [block~ 512 4]) if stopping/restarting the DSP.
> 
> x->x_fill = prologphase ? x->x_endbuf - (x->x_hop - prologphase * re_parentvecsize) : x->x_endbuf;
> 
> The change above might solve the problem.
> 
> I'm not 100 % sure. I'm currently testing the fix on Spaghettis < https://github.com/Spaghettis/Spaghettis/compare/dev >.
> 
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