[PD] Switch and ramp and accurate timing

[Roman Haefeli]

On Mon, 2007-05-07 at 01:02 +0200, Frank Barknecht wrote:
> Hi,
> 
> hm, unfortunately the "switch and ramp" technique is not usable for
> signals started from clock-delayed messages (as in [vline~]) because
> [snapshot~] is too slow to react. 

this might be old news for you guys, frank and simon, but when this
technique is used on table based samplers, there is no need for a
[vsnapshot~] at all. since you know the actual position of [vline~]
(using timer) and the startpoint for the next cycle, you can simply look
up these values with [tabread] (or [tabread4] to get some kind of a fake
subsample accuracy). 
like this, you do not need any [snapshot~], which lacks support of
'clock-delayed' message nor any [vsnaphot~], which would require the
signal to be delayed by one block, because of the signal->message-signal
conversion problem (as described by IOhannes). 

though, this approach might not work for synthesizers.....

roman




	
		
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