[PD] regression testing WAS Re: [psql] object hand-holding

Mathieu Bouchard matju at artengine.ca
Sun Dec 30 00:18:47 CET 2007

On Mon, 24 Dec 2007, Martin Peach wrote:

> OK, but that's not called tristate, and "dual-rail" usually means having two 
> power supplies (e.g. plus and minus 5V instead of just 5V).

I don't know, I only read that somewhere quickly, just to verbalise again 
what I had learnt before and didn't remember the vocabulary for. Seems 
like at least one text calls it "dual-rail" and that it considers the term 
to be more general than power supply.

> What you are describing is like a two-wire serial setup where the data 
> on the second wire is only considered valid when the first wire is high. 
> It's not clockless, in fact the first wire is usually named "Clock".

A clockless system is one in which the flow is not regular. In that case, 
the synchronisation is still made along one wire that one doesn't really 
have any reason to name it something else than "clock", except for the 
fact that it's not regular and not coming from a component called a clock. 
Instead the rate is determined holistically. It's more like a very 
fine-grained CTS/RTS line.

> The clock frequency is affected by temperature, but it's still a clock. I 
> guess you're saying that a crystal oscillator is a clock and a RC oscillator 
> is not, which is a new meaning to me.

I don't know why, but if you use the whole CPU as being its own clock, 
it's not called a clock anymore.

> Even crystal oscillators are affected by temperature because the crystal 
> gets bigger as it warms up, if you want a stable frequency you need to 
> run it in temperature-controlled oven.

The temperature features are not an essential element of the "clockless" 
architecture I'm talking about, it's just an example of what they are good 
at. Crystal clocks are designed to change as little as possible, but it 
doesn't make much sense, as computers could both run faster and be more 
reliable, if the clock rate was chosen according to the temperature.

> If you have 9 wires you have 512 possible states, so it's wasteful if 256 of 
> them mean the same thing.

So why are serial protocols locked to something made of 10 bits that have 
only 256 or 257 distinct states? That's even more wasteful. If serial 
protocols like that are ok, what's the problem with having parallel 
protocols like that? Anyway, I think that people want to use power-of-two 
number of states in those machines, and you can't do that and a WAIT 
state easily, without duplicating the WAIT state to the point that 50% of 
the states are WAIT. It's just not worth to optimise this.

> That may be why the two-wire system is not much used. Cpus often have a 
> line to indicate if the data on the bus is valid or not

This is the kind of line I'm talking about, exactly.

> And you can add wait states to memory access cycles so the ram has time 
> to handle the data, which involves using a WAIT line to hold off the cpu 
> until the time has elapsed.

Problem with WAIT lines on RAM is that they have to be synched with CPU 
clocks, which means that all times have to be rounded up to next integer 
number of clock cycles...

> To be bulletproof you would need to schedule an external interrupt to 
> kill the process in case of infinite loop. Maybe the pd watchdog could 
> be adapted to do that? At the moment it doesn't seem to care if I banged 
> an [until] because the connection to the gui is still functional.

Huh, is it still functional?... I don't think so.

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| Mathieu Bouchard - tél:+1.514.383.3801, Montréal QC Canada

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