[PD] phasor~ and osc~ right inlet: exact timing

Mike Moser-Booth mmoserbooth at gmail.com
Tue Apr 20 04:17:17 CEST 2010

Hey Frank,
Frank Barknecht wrote:
> Hi,
> On Mon, Apr 19, 2010 at 09:21:35AM +0200, Frank Barknecht wrote:
>> On Sun, Apr 18, 2010 at 11:42:45AM -0400, Mike Moser-Booth wrote:
>>> Frank, I was looking at your comparison patch and noticed you took
>>> the [+~ 2] out. The reason I put this in is because [wrap~] converts
>>> 0 to 1, so if you reset the phase to 0 you'll end up starting at the
>>> end instead of the beginning. 
>> Yeah, that's a nasty old bug of wrap~. Miller, when can we get a fix? :)
>> I simplified it away here just to concentrate on the other aspect.
>> Btw.: vanilla's [wrap] in Pd can be used to replace the modf-expr you
>> use after the phase inlet - [wrap] for messages is even correct for 0. :)
> Oh, and I hope you don't mind, but I added a simplified, expr-less
> version to the rj library as s_vphasor as attached (giving you credit).
I am totally okay with this! Thanks. :-)
> There I added the 2 to the phase value sent into the vline~ to save on
> signal addition object - iDevices are slow. :)
Even better.

I wasn't sure about vanilla's [wrap]. I'm using extended, and it uses 
zexy's instead. I wanted to make sure this worked in both vanilla and 
extended, and since you can't do [vanilla/wrap] I just made it with 
[expr]. But I guess with no arguments they work the same. Good to know, 


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