[PD] phasor~ and osc~ right inlet: exact timing

[Frank Barknecht]

On Sun, Apr 18, 2010 at 01:28:02PM +0200, Matteo Sisti Sette wrote:
> > Actually I meant two write "take a [samphold~] of the original
> > phasor". Taking a snapshot~ or rather, a vsnapshot~ is something
> > I have also tried, but it gives the wrong results. See attached
> > example for a comparison of [vsnapshot~]->[vline~] with
> > Mike's [samphold~] solution (which I simplified a bit). Lesson
> > to learn:  [vsnapshot~]->[vline~]
> > won't do what you may expect it to do.
> 
> Very very interesting. Basically you have to take into account that
> vsnapshot~ samples the signal with a delay of one block~ (and it
> couldn't be otherwise), which renders it useless for the phasor~
> accurate reset application.

Pd alternates message and dsp computations. So the order here is:
vsnapshot~ analyses dsp, then produces a message, then vline~ gets this
one during the following message pass which is already too late to
change its own signal result in the previous block. Duh.

So while both vsnapshot~ and vline~ are subsample-accurate in a block, the
combination is not. The samplehold~ approach also uses vline~ to
schedule an accurate impulse, but as samphold~ works entirely in the
signal realm, no delaying message pass is needed in between.

Ciao
-- 
Frank