[PD] phasor~ and osc~ right inlet: exact timing

[Matteo Sisti Sette]

 > Actually I meant two write "take a [samphold~] of the original
 > phasor". Taking a snapshot~ or rather, a vsnapshot~ is something
 > I have also tried, but it gives the wrong results. See attached
 > example for a comparison of [vsnapshot~]->[vline~] with
 > Mike's [samphold~] solution (which I simplified a bit). Lesson
 > to learn:  [vsnapshot~]->[vline~]
 > won't do what you may expect it to do.

Very very interesting. Basically you have to take into account that 
vsnapshot~ samples the signal with a delay of one block~ (and it 
couldn't be otherwise), which renders it useless for the phasor~ 
accurate reset application.
The [samphold~] solution is brilliant.

I attach a test patch to demonstrate the one-block delay of vsnapshot~ 
(it could already be appreciated in your patch but here it is "isolated")


-- 
Matteo Sisti Sette
matteosistisette at gmail.com
http://www.matteosistisette.com
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